The present invention relates to a semiconductor memory device, and more particularly to a method and circuit for controlling a write driver, which amplifies data inputted from an exterior and provides the amplified data to a memory cell in a write operation.
As generally known in the art, a semiconductor memory device includes a write driver, which amplifies data inputted from an exterior and transmits the amplified data to a local input/output line in a write operation. The operation of such a write driver is controlled by a write driver control circuit as shown in FIG. 1.
In detail, as shown in FIG. 1, a write driver control circuit 10 includes four latch units 11 to 14, and a write driver 20 includes two driver units 21 and 22. The constructions and operations of the write driver control circuit 10 and write driver 20 will now be described with reference to FIGS. 1 and 2.
The first latch unit 11 may include PMOS transistor P1, NMOS transistor N1, NMOS transistor N2, and two inverters INV1 and INV2. The PMOS transistor P1 is turned on by data transferred from a global input/output bar line GIOB and configured to raise the voltage of node ND1 to the level of a power supply voltage VDD. The NMOS transistor N1 is turned on by the data transferred from the global input/output bar line GIOB and configured to connect the node ND1 with the NMOS transistor N2. The NMOS transistor N2 is turned on by a write driver enable signal BWEN and configured to lower the voltage of the node ND1 to the level of a ground voltage VSS. The inverters INV1 and INV2 latch data transferred to the node ND1, and output the latched data DATA_LATB.
The first latch unit 11 having such a construction latches data transferred from the global input/output bar line GIOB by using the write driver enable signal BWEN, thereby securing a timing margin for data transmission.
The second latch unit 12 may include PMOS transistor P2, NMOS transistor N3, NMOS transistor N4, and two inverters INV3 and INV4. The PMOS transistor P2 is turned on by data transferred from a global input/output true line GIOT and configured to raise the voltage of node ND2 to the level of the power supply voltage VDD. The NMOS transistor N3 is turned on by the data transferred from the global input/output true line GIOT and configured to connect the node ND2 with the NMOS transistor N4. The NMOS transistor N4 configured to lower the voltage of the node ND2 to the level of the ground voltage VSS by using the write driver enable signal BWEN. The inverters INV3 and INV4 latch data transferred to the node ND2, and output the latched data DATA_LAT.
The second latch unit 12 having such a construction latches data transferred from the global input/output true line GIOT by using the write driver enable signal BWEN, thereby securing a timing margin for data transmission.
The third latch unit 13 may include PMOS transistor P3, NMOS transistor N5, NMOS transistor N6, and inverters INV5, INV6, INV7 and INV8. The PMOS transistor P3 is turned on by a precharge control signal PCG and configured to raise the voltage of node ND3 to the level of the power supply voltage VDD. The NMOS transistor N5 is turned on by a delayed write driver enable signal DBWEN, which has been delayed to be enabled at a point of time when the latched data DATA_LATB and DATA_LAT are outputted, and configured to connect the node ND3 with the NMOS transistor N6. The NMOS transistor N6 is turned on by the latched data DATA_LATB and configured to lower the voltage of the node ND3 to the level of the ground voltage VSS. The inverters INV5 and INV6 latch data transferred to the node ND3 and output the latched data PRE_DRV. The inverters INV7 and INV8 invert and delay the latched data PRE_DRV and output an inverted latch signal LATB and a driver signal DRV, respectively.
The third latch unit 13 having such a construction latches data transferred to the node ND3 by using the delayed write driver enable signal DBWEN, the precharge control signal PCG, and the signal DATA_LATB outputted from the first latch unit 11, thereby generating the inverted latch signal LATB and driver signal DRV to control the operation of the write driver.
The fourth latch unit 14 may include PMOS transistor P4, NMOS transistor N7, NMOS transistor N8, and inverters INV9, INV10, INV11 and INV12. The PMOS transistor P4 is turned on by the precharge control signal PCG and configured to raise the voltage of node ND4 to the level of the power supply voltage VDD. The NMOS transistor N7 is turned on by the delayed write driver enable signal DBWEN and configured to connect the node ND4 with the NMOS transistor N8. The NMOS transistor N8 is turned on by the latched data DATA_LATB and configured to lower the voltage of the node ND4 to the level of the ground voltage VSS. The inverters INV9 and INV10 latch data transferred to the node ND4 and output the latched data PRE_DRVB. The inverters INV11 and INV12 invert and delay the latched data PRE_DRVB, and output a latch signal LAT and an inverted driver signal DRVB, respectively.
The fourth latch unit 14 having such a construction latches data transferred to the node ND4 by using the delayed write driver enable signal DBWEN, the precharge control signal PCG, and the signal DATA_LAT outputted from the second latch unit 12, thereby the fourth latch unit 14 is configured to generate the latch signal LAT and inverted driver signal DRVB to control the operation of the write driver.
The first driver unit 15 may include PMOS transistor P5 and NMOS transistor N9. The PMOS transistor P5 is turned on by the latch signal LAT and configured to raise the voltage of a local input/output true line LIOT to the level of a core voltage VCORE, and the NMOS transistor N9 is turned on by the driver signal DRV and configured to lower the voltage of the local input/output true line LIOT to the level of the ground voltage VSS.
The first driver unit 21 having such a construction amplifies and transmits data of the global input/output true line GIOT to the local input/output true line LIOT, by using the latch signal LAT and driver signal DRV.
The second driver unit 22 may include PMOS transistor P6 and NMOS transistor N17. The PMOS transistor P6 is turned on by the inverted latch signal LATB and configured to raise the voltage of a local input/output bar line LIOB to the level of the core voltage VCORE; and the NMOS transistor N17 is turned on by the inverted driver signal DRVB and configured to lower the voltage of the local input/output bar line LIOB to the level of the ground voltage VSS.
The second driver unit 22 having such a construction amplifies and transmits data of the global input/output bar line GIOB to the local input/output bar line LIOB, by using the inverted latch signal LATB and inverted driver signal DRVB.
As described above, the write driver control circuit 10 of FIG. 1 latches data of a pair of global input/output lines GIOT and GIOB; and the write driver 20 drives a pair of local input/output lines LIOT and LIOB by using the signals LAT, PRV, LATB and PRVB outputted from the write driver control circuit 10.
However, because the write driver control circuit 10 generates the signals LAT, PRV, LATB and PRVB to control the operation of the write driver 20 by latching data of the pair of global input/output lines GIOT and GIOB through the four latch units 11 to 14, an area occupied by the write driver control circuit 10 may require a burdensome increase in a semiconductor memory device.
In addition, since the write driver control circuit 10 as shown in FIG. 1 controls the write driver 20 by latching data transmitted from the pair of global input/output lines GIOT and GIOB through four latch units 11 to 14, there is a potential problem in that a large amount of current may be consumed due to such a latching operation in a write operation.